The present invention relates to electronic circuits, and more particularly, to delay-locked loops.
A backplane is a circuit board that is used to connect printed circuit board cards together to make up a complete computer system. Data transmitted in backplane data communications systems is controlled by a clock signal that is generated by a clock generator. A clock generator can be implemented using a frequency synthesizer that can generate a range of clock signal frequencies. A frequency synthesizer is typically based on a phase-locked loop (PLL).
Current implementations of frequency synthesizers typically have a PLL circuit that includes a voltage controlled oscillator (VCO). In many applications, a frequency synthesizer is required to comply with stringent jitter specifications. As a result, the design of the PLL has to be very well isolated from on-chip supply noise. Also, the PLL should have a high-quality VCO to minimize jitter. However, most high-quality VCO's consume a large amount of power and a large amount of silicon die area.
Alternatively, a frequency synthesizer can be based on a delay-locked loop (DLL). DLL-based frequency synthesizers provide exceptional phase noise performance. However, a DLL frequency synthesizer can only generate an output frequency that is the product of an integer times the frequency of an input reference clock signal.
Therefore, it would be desirable to provide a low noise frequency synthesizer that can provide a periodic output signal having a frequency that is the product of an input signal frequency and a fractional number.